This application claims priority from Japanese Patent Application Numbers JP2007-30797 filed on Feb. 9, 2007 and JP2008-006276 filed on Jan. 15, 2008, the contents of which are incorporated herein by reference in their entirety.
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
As an embodiment of a conventional semiconductor device, a structure of the following NPN transistor 281 has been known. As shown in FIG. 25, an N type epitaxial layer (hereinafter, referred to as EPI) 283 is formed on a P type semiconductor substrate 282. In the EPI 283, P type buried diffusion layers (hereinafter, referred to as buried layers) 284 and 285, which are diffused in a vertical direction from a surface of the substrate 282, and P type diffusion layers 286 and 287, which are diffused from a surface of the EPI 283, are formed. Moreover, the EPI 283 is divided into a plurality of island regions (hereinafter, referred to as islands) by isolation regions (hereinafter, referred to as ISOs) 288 and 289, which are formed by connecting the buried layers 284 and 285 with the diffusion layers 286 and 287, respectively. In one of the islands, the NPN transistor 281 is formed, for example. The NPN transistor 281 is mainly formed of an N type buried layer 290 used as a collector region, a P type diffusion layer 291 used as a base region and an N type diffusion layer 292 used as an emitter region. Moreover, the buried layers 284 and 285 are diffused by subjecting the substrate 282 to a dedicated heat treatment. Meanwhile, the diffusion layers 286 and 287 are also diffused by subjecting the substrate 282 to a dedicated heat treatment. By these thermal diffusion steps, the buried layer 284 and the diffusion layer 286 are connected with each other to form the ISO 288, and the buried layer 285 and the diffusion layer 287 are connected with each other to form the ISO 289. This technique is described, for instance, in Japanese Patent Application Publication No. Hei 9 (1997)-283646 (Pages 3, 4 and 6, FIGS. 1 and 5 to 7).
As described above, in the conventional semiconductor device, the thickness of the EPI 283 is determined by taking account of the breakdown voltage of the NPN transistor 281. For example, in the case where a power semiconductor element and a control semiconductor element are formed on the same substrate 282, the thickness of the EPI 283 is determined in accordance with breakdown voltage characteristics of the power semiconductor element. Moreover, the buried layers 284 and 285 expand upward from the surface of the substrate 282 into the EPI 283. Meanwhile, the P type diffusion layers 286 and 287 expand downward from the surface of the EPI 283. This structure allows lateral diffusion widths W23 and W24 of the buried layers 284 and 285 to be increased with the increase of the upward expansion amounts thereof. Accordingly, this structure has a problem that it is difficult to reduce the size of formation regions of the ISOs 288 and 289.
In the conventional semiconductor device, the EPI 283 is formed on the substrate 282. The NPN transistor 281 is formed in a region defined by the ISOs 288 and 289 in the EPI 283. Moreover, the EPI 283 is a region with a low concentration of the N type impurity. With the alignment accuracy in the above configuration, a formation region of the buried layer 284 or the diffusion layer 291 is shifted, so that a distance L9 between the buried layer 284 and the diffusion layer 291 is shortened. Thus, a region in which a depletion layer expands is reduced in size. Accordingly, in the NPN transistor 281, short-circuit is likely to occur between the base region and each of the ISOs 288 and 289. Thus, the conventional semiconductor device has a problem that it is difficult to obtain desired breakdown voltage characteristics. Moreover, the conventional semiconductor device has another problem that a variation in the distance L9 causes the breakdown voltage characteristics of the NPN transistor 281 to be unstable.
Moreover, in the conventional semiconductor device, it is required to secure a certain distance for the distance L9 between the diffusion layer 291 and the buried layer 284 in order to achieve a desired breakdown voltage of the NPN transistor 281. Similarly, it is also required to secure a certain distance for a distance L10 between the diffusion layers 291 and 286. However, a problem arises that the increase in the lateral diffusion width W23 and also a lateral diffusion width W25 of the buried layer 284 and the diffusion layer 286 makes it difficult to reduce the device size of the NPN transistor 281.
Moreover, in a conventional method of manufacturing the semiconductor device, the above-described two thermal diffusion steps are performed to connect the buried layers 284 and 285 with the diffusion layers 286 and 287, respectively. This manufacturing method allows the lateral diffusion widths W23 and W24 of the buried layers 284 and 285 to be increased with the increase of the upward expansion amounts thereof. Moreover, by the thermal diffusion steps, the N type buried layer 290 also expands toward the surface of the EPI 283. As a result, a problem arises that it is difficult to reduce the size of the formation regions of the ISOs 288 and 289, and also to reduce the device size of the NPN transistor 281.
Description will be further given of a structure in which NPN transistors 301 and 302 are adjacent to each other with an ISO 303 interposed therebetween as shown in FIG. 26. A ground voltage (GND) is applied to a collector region of the NPN transistor 301, and a power supply voltage (Vcc) is applied to a collector region of the NPN transistor 302. In this case, in the NPN transistor 302, a reverse bias is applied to a PN junction region of the P type ISO 303 and a P type semiconductor substrate 304 with an N type EPI 305 and an N type buried layer 306. Moreover, a depletion layer spreads from the PN junction region toward the P type ISO 303 and the P type substrate 304.
In this event, when an impurity concentration in an overlapping region of a P type buried layer 307 and a P type diffusion layer 308 is lowered in the ISO 303, the depletion layer spreads into the NPN transistor 301 as indicated by a dotted line. A problem here is that, when the spreading depletion layer reaches an N type buried layer 309, the collector regions of the NPN transistors 301 and 302 are short-circuited, and thereby, a leak current is caused. In order to prevent the occurrence of leak current, it is required to more widely diffuse the buried layer 307 and the diffusion layer 308 to increase the impurity concentration in the overlapping region. In this case, however, a diffusion width W26 of the buried layer 307 and a diffusion width W27 of the diffusion layer 308 are increased. Thus, a problem arises that it is difficult to reduce the device size of each of the NPN transistors 301 and 302.